AND Gate
An AND gate has two or more input voltages or signals and a single output voltage or signal like any other gate. This gate is called an AND gate because the output voltage is high only if all input voltages are high. For example, if both input voltages of an AND gate with two inputs are high, its output voltage will also be high.
Working principle of AND gate
How the AND gate works can be easily understood from the figure below. In a circuit, two switches A and B are connected in series. obviously,
- The bulb does not turn on when both switches are in the off position; In this case, the output is zero, i.e., no output is available.
- The bulb does not turn on when either switches A or B is off and the other is on; In this case, the output is zero, i.e., no output is available.
- Only when both switches are in the ON position together does the bulb turn on, i.e., output is available.
So this circuit works like an AND gate.
AND gate in electronic circuit
The figure shows an electronic AND gate with two inputs. The simplified form of this circuit is also shown.
The input voltages are denoted by A and B and the output voltage is denoted by Y. Suppose, the two possible states of the input voltage are low (say, 0V) and high (say, 5V). Resistor RL and VCC (=5V) batteries are permanently connected to the circuit. The gate can be in any one of the following four states.
- A is low and B is low: In this case the output voltage is low. As shown in the figure, if A and B are low, the two diodes are forward-biased for VCC, i.e., the two diodes are in a conduction state. This results in the same voltage across A, B, and Y. That is, Y is also low.
- A is low and B is high: In this case the output voltage is low. According to the figure, if B is high, then the diode connected to B is reverse biased, i.e., this diode is non-conducting. But if A is low then the diode connected to A is conducting for VCC. This results in the same voltage across A and Y, i.e., Y is low.
- A is high and B is low: In this case the output voltage is low. According to the figure, if A is high, then the diode connected to A is reverse biased, i.e., this diode is non-conducting. But if B is low then the diode connected to B is conducting for VCC. This results in the same voltage across B and Y, i.e., Y is low.
- A is high and B is high: In this case the output is high. According to the figure, if A and B are high, then the two diodes are in reverse bias, i.e., the two diodes are non-conducting. This causes no current to flow through RL. So, Y stays high for VCC.
Note: By comparing the circuit diagrams of the OR gate and AND gate, it can be seen that an OR gate will easily become an AND gate if 1. The diodes are reversed, and 2. Instead of grounding one end of the load resistor RL, the appropriate voltage (VCC) is applied there.
Truth table
A closer look at the truth table shows that if both inputs are 1, then the output is 1. That is, the state of Y is 1 if the states of A and B are 1. In other words, the AND gate is an ‘all-or-nothing’ gate; The output state is 1 if all the input states are 1, otherwise, the output state is 0.
| A | B | Y |
|---|---|---|
0 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
0 |
1 |
1 |
1 |
Symbol
The AND gate symbol is shown in the figure. Digital circuits are drawn using this symbol.
Boolean algebra related to AND gate
In Boolean algebra, the AND process is denoted by the symbol ‘ · ‘. The Boolean algebraic equation for the AND gate shown in the figure is,
Y = A · B or, AB
When A = 0 = B, then Y = 0 · 0 = 0
When A = 0 and B = 1, then Y = 0 · 1 = 0
When A = 1 and B = 0, then Y = 1 · 0 = 0
When A = 1 = B, then Y = 1 · 1 = 1
Figure shows the circuit of an AND gate with three inputs, symbols, Boolean algebraic equation and truth table.
| A | B | C | Y |
|---|---|---|---|
0 |
0 |
0 |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
1 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
1 |
0 |
1 |
1 |
0 |
0 |
1 |
1 |
1 |
1 |
Digital signal
The figure shows the waveforms of two digital signals A and B as an example.
- In case of OR gate: (A + B = Y) Obviously, both signals A and B are at low level i.e., 0-level during these two-time intervals—EF and GH. Hence, the output Y of the OR gate will be at the 0 level during these two intervals. All other recesses have either A or B, or both A and B signals at the 1-level. Hence, Y will also be at the 1-level. This output waveform is shown in Fig.
- In the case of AND gate: (A · B = Y) In this case, both signals A and B are at a high level i.e., 1-level during time intervals CD, FG, and IJ. So, during these intervals, the output of the AND gate will be Y and 1-level. All other recesses have either A or B, or both A and B signals at the 0-level. As a result, Y will also be at the 0 level. This output waveform is shown at the bottom of the figure.
Special note
- OR, AND, and NOT gates are called basic logic gates. Because any other logic gate is some combination of these three basic gates.
- Not all logic gates can be constructed using any of the three basic gates. For example, an AND gate or a NOT gate cannot be obtained by combining multiple OR gates. However, NOR and NAND gates can be made by combining OR, AND, and NOT gates. The peculiarity of this dual gate is that, given a large number of NOR data, all kinds of logic gates can be made by specially combining them—as is the case with NAND gates. This is why NOR and NAND gates are called universal logic gates, although neither of them are fundamental gates.
- De Morgan’s theorem is used to construct various logic gates using multiple basic gates.
De Morgan’s theorem
- (A ∪ B)’ = A’ ∩ B’
- (A ∩ B)’ = A’ ∪ B’
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